A Reconfigurable Pipelined Idct for Low-energy Video Processing
نویسندگان
چکیده
In video processing, average data rates are often significantly lower than a given maximum possible rate. Consequently, VLSI systems that are capable of processing video streams at the maximum data rates specified in video standards can be excessively dissipative at low data rates. Such inefficiencies are particularly pronounced in heavily pipelined designs, in which registers account for the bulk of the energy dissipation. This paper describes a novel methodology for designing reconfigurable pipelined datapaths that achieve very low energy dissipation by adapting their structures to their computational requirements. In our reconfigurable datapaths, energy is saved by disabling and bypassing an appropriate number of dissipative pipeline stages whenever data rates are low. To evaluate our methodology, we designed reconfigurable multiplier-accumulator (MAC) based inverse discrete cosine transform (IDCT) modules for MPEG-2 MP@ML. Our IDCT pipelines were dynamically reconfigurable based on the the number of nonzero coefficients per block and picture size. In comparison with corresponding IDCT implementations that used conventional pipelines, our reconfigurable IDCT modules dissipated about 12-65% less energy.
منابع مشابه
Fine-grain real-time reconfigurable pipelining
In many computations, average data rates are often significantly lower than the peak rate possible. Consequently, VLSI systems capable of processing data at a maximum specified rate can be excessively dissipative when data rates are low. Such inefficiencies are particularly pronounced in heavily pipelined designs, in which registers account for the bulk of energy dissipation in a system. This p...
متن کاملImplementation of a 2-d 8x8 Idct on the Reconfigurable Montium Core
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R © processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementat...
متن کاملA Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC
In this paper, we present an area-efficient 4/8/16/32-point inverse discrete cosine transform (IDCT) architecture for a HEVC decoder. Compared with previous work, this work reduces the hardware cost from two aspects. First, we reduce the logical costs of 1D IDCT by proposing a reordered parallel-in serial-out (RPISO) scheme. By using the RPISO scheme, we can reduce the required calculations for...
متن کاملA full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard
High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65 nm ...
متن کاملDesign and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)
Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2001